Analog-to-digital converters (ADCs) are widely used in communication systems to interface analog and digital circuits. While the speed, power, and area of digital circuits directly benefit from the decreasing channel length of CMOS devices, analog circuits suffer from reduced headroom, lower intrinsic gain, and higher device mismatch. Consequently, it has been increasingly difficult to design high-speed and low-power pipelined ADCs using conventional op amps.

This work presents a pipelined ADC that employs novel "charge-steering" op amps to relax the trade-offs among speed, noise,and power consumption. Such op amps afford a fourfold increase in speed and a twofold reduction in noise for a given power consumption and voltage gain. Using a new clock gating technique, the ADC digitally calibrates the nonlinearity and gain error at full speed. A prototype realized in 65-nm CMOS technology achieves a resolution of 10 bits with a sampling rate of 800 MHz, a power consumption of 19 mW, an SNDR of 52.2 dB at Nyquist, and an FoM of 53 fJ/conversion-step. A new background calibration technique is also proposed to accommodate temperature and supply variations.

High-speed analog-to-digital converters (ADCs) are at the heart of many applications such as digital communication, video, and instrumentation. However, the power efficiency of ADCs tends to degrade as higher speeds and/or resolutions are sought. In this research, we introduce a low-power high-speed pipelined ADC architecture that employs a precharged resistor-ladder digital-to-analog converter (RDAC) and a multi-bit front end with a low-gain op amp. Avoiding the need for op amp nonlinearity calibration, the ADC only computes the gain errors and corrects them in the digital domain. In addition, RDAC simplifies the calibration logic and enables high-speed gain error calibration, thus correcting for the incomplete settling of the MDACs. Using simple differential pairs with gains of about 5 as op amps and realized in 65-nm CMOS technology, the 10-bit ADC consumes 36 mW at a sampling rate of 1 GHz and exhibits an FOM of 70 fJ/conv.-step.

A critical issue in the design of high-speed ADCs relates to errors that result from comparator metastability. Studied for only flash architectures, this phenomenon assumes new dimensions in pipelined converters, creating far more complex error mechanisms. In this dissertation, we present a comprehensive analysis of comparator metastability effects in pipelined ADCs and develop a method to precisely predict the error behavior for a given input signal p.d.f.

Recent studies indicate that the input/output (I/O) bandwidth of serial links must increase by 2 to 3 times every two years so as to keep up with the demand for higher data rates. In order to manage such bandwidths with reasonable power consumption, an efficiency of around 1 mW/Gb/s for the overall transceiver is targeted, necessitating a much smaller value for each building block.

The latches, demultiplexers and frequency dividers comprising a broadband receiver consume the lion’s share of the power. Current-steering circuits run at high speed but draw considerable static power, whereas rail-to-rail CMOS circuits can avoid static bias but at the cost of speed.

This work describes the development of a 25-Gb/s clock and data recovery (CDR) circuit and a deserializer that, through the use of “charge steering” and other innovations, achieve a twenty-fold reduction in the power dissipation with respect to the prior art. Realized in 65-nm CMOS technology, an experimental prototype draws 5-mW from a 1-V supply, exhibiting an integrated clock jitter of 1.52 ps,rms and a jitter tolerance of 0.5 unit interval (UI) at a jitter frequency of 5 MHz.

In order to increase the data rate in a communication link, the modulation scheme can incorporate a high-order constellation but at the cost of tighter linearity and/or phase noise requirements. For example, if QPSK is replaced with 16QAM, the data rate increases by a factor of 2 while the transmitter output level must be backed off by 6 to 8 dB. Among various transmitter linearization techniques, two are based on signal decomposition and have shown promise for integration: polar modulation and outphasing. However, the former must deal with delay mismatches between the phase and amplitude paths and the leakage of the phase signal to the output, a serious issue at millimeter-wave frequencies. Outphasing faces two drawbacks: the loss due to the output power combining operation, especially if realized on-chip, and the undesirable coupling between two power amplifiers through the combiner.

This work describes a transmitter linearization technique that is suited to beamforming arrays. Two or more constant-amplitude outphasing signals are transmitted by different antennas and combined in space, thus reconstructing the original amplitude and phase-modulated signals. The proposed approach provides a favorable trade-off between spectral and power efficiencies. Additionally, the directivity of the new approach translates to a narrow spatial angle for correct signal reception, yielding a high level of security. A dual-transmitter prototype fabricated in 65-nm CMOS technology and designed for the 60-GHz band produces a 16QAM output of +9.7 dBm with 11% efficiency and an EVM of -18.8 dB.

In order to reduce the pin count of chips and the complexity of the routing on printed-circuit boards and backplanes, it is desirable to replace a large number of parallel channels with a few serial links. Such a transformation can also potentially save significant power because it maintains the I/O voltage swings and termination impedances relatively constant. It is therefore plausible that data rates approaching 20 Gb/s will become common in the near future. At these speeds, the loss of FR4 boards poses a great challenge, requiring heavy equalization. From circuit design point of view, it is simpler to employ linear equalization (in the transmitter and the receiver), but from system design point of view, two serious issues make this approach unattractive: the amplification of crosstalk and the lack of ability to equalize for impedance discontinuities (sharp notches in the channel frequency response). In an optimum, yet practical system, one would place 4 to 5 dB of linear equalization in the transmitter and a similar amount in the receiver, and perform the remaining equalization by means of a decision-feedback equalizer (DFE), thus alleviating both issues.

 This work presents a 20-Gb/s serial link equalizer capable of compensating 24 dB of channel loss at 10 GHz. It consists of a linear equalizer with 9 dB of boost and a 1-tap speculative half-rate DFE. It generates an output with a BER less than 10^-12 and an eye opening of 0.32 UI. Fabricated in 90-nm CMOS technology, the prototype draws 40 mW from a 1-V supply at 20 Gb/s.

The design of high-speed, high-resolution ADCs continues to present greater challenges as the device dimensions and supply voltages are scaled down. While generic issues such as capacitor mismatch provided the impetus for earlier calibration techniques, deep-submicron low-voltage technologies have made it increasingly difficult to realize high-gain op amps, requiring additional calibration that corrects for gain error and nonlinearity. With the declining intrinsic gain of transistors, it is expected that the notion of fast-settling, low-voltage, high-gain op amps will eventually become obsolete. This research explores the use of low-gain op amps in high-performance pipelined ADCs. A new architecture incorporates a blind LMS calibration algorithm to correct for capacitor mismatches, residue gain error, and op amp nonlinearity. The calibration applies 128 levels and their perturbed values, computing 128 local errors across the input range and driving the mean square of these errors to zero. Fabricated in 90-nm digital CMOS technology, the ADC achieves a DNL of 0.78 LSB, an INL of 1.7 LSB, and an SNDR of 62 dB at an analog input frequency of 91 MHz while consuming 348 mW from a 1.2-V supply.

Equalization and Clock and Data Recovery Techniques for Serial-Link Receivers

This research deals with the design of receivers for serial-link applications. Various approaches to implementing continuous-time equalization and clock and data recovery functions are introduced that overcome technology limitations. The techniques greatly enhance the speed and channel loss compensation capabilities of the receiver while providing complete adaptability. Two techniques, namely, reverse scaling and series peaking, are proposed to ease the trade-offs in equalizer design. Dual- and triple-loop adaptation schemes are also presented for stand-alone equalizers and a merged equalizer/CDR circuit, respectively. The loops enable adaptation to transmitter swing variations and a range of channel loss profiles. The proposed techniques have been experimentally verified using two prototypes - a stand-alone equalizer and a merged equalizer/CDR circuit. The prototypes are implemented in 0.13-um CMOS technology and operate at 10 Gb/s while adapting to FR4 trace lengths up to 24 inches. The stand-alone equalizer and the merged equalizer/CDR circuit consume 25 mW and 133 mW from 1.2-V and 1.6-V supplies, respectively.

A New Receiver Architecture for Multiple-Antenna Systems

To minimize the power consumption and the area of a dual-antenna MIMO receiver one may naturally conceive the arrangement where a single receive path including radio frequency and baseband sections, is shared between the two antennas, and the switching is performed at a rate of at least the RF channel bandwidth. This dissertation identifies two fundamental issues with this approach. First, the switching rate must accommodate all interferers, since for any switching rate there exists an interferer that corrupts the desired signal. Second, channel selection, even for minimum switching rate, will corrupt the receiver output and subsequent switching to recover each antenna signal will not undo this corruption. A new dual-antenna receiver architecture is introduced that employs quadrature down conversion and complex filtering in a low-IF topology. The principle introduced in this architecture is based on down converting the two antenna signals such that one appears in the positive intermediate frequency range and the other in the negative intermediate frequency range, thus allowing their summation and hence digitization by only one pair of A/D converters. The proposed architecture reduces the number of A/D converters by a factor of two and is versatile enough to be used with antenna diversity, beamforming, as well as MIMO systems. The dual-antenna receiver was implemented for IEEE 802.11a standard with the RF signal at 5.39 GHz. Fabricated in a standard digital 0.18 μm CMOS technology the dual-antenna receiver, whose active area measures 1.9 mm ? 1.3 mm, meets the IEEE 802.11a sensitivity requirement for a 64QAM OFDM signal with at least 7 dB of margin.

Broadband Circuits for High-Speed Communication Systems

This dissertation pushes CMOS technology to higher speeds, enabling data rates of 10 Gb/s and beyond to be accommodated. The integration of these circuits with digital back-end circuits will allow lower power, higher density, and lower cost. This work describes the design of broadband devices and circuits for data communication systems. This includes high-speed drivers in the transmitter, broadband amplifiers in the receiver, and ESD protection be iznterface between these circuits and the physical medium. New broadband techniques such as active feedback, negative capacitance cancellation, and T-coil peaking are introduced. These techniques overcome the technology limitations by providing broad bandwidth and perfect impedance matching. Fabricated in a mixed-signal 0.18-um CMOS technology, a limiting amplifier incorporates active feedback, inductive peaking, and negative Miller capacitance to achieve a voltage gain of 50~dB, a bandwidth of 9.4 GHz and a sensitivity of 4.6 mV-pp for BER of 10^-12 while consuming 150 mW. A 10-Gb/s laser and modulator driver employs T-coil peaking and negative impedance conversion to achieve operation at 10 Gb/s while delivering a current of 100 mA to 25-Ohm lasers or a voltage swing of 2 V-pp to 50-Ohm modulators with a power dissipation of 675mW. A broadband technique using monolithic T-coils is applied to ESD structures for both input and output pads. The prototypes achieve operation at 10 Gb/s while providing a return loss of -20 dB at 10 GHz. The human-body model tolerance is 1000 V for the input structure and 800-900 V for the output structure. Finally, a 40-Gb/s CMOS amplifier employs a cascade of triple-resonance stages achieves a total gain of 15 dB.

Circuit Techniques for High-Speed Communication Systems

The rapid increase in the demand for broadband data communication systems has motivated extensive research on higher-speed, higher-integrated solutions with lower cost and lower power consumption. This research deals with architecture and circuit design as well as theoretical modeling for such applications. First, we propose an analysis of regenerative dividers that predicts the required phase shift or selectivity for proper operation. A divider topology is introduced that employs resonance techniques by means of on-chip spiral inductors to tune out the device capacitances. Configured as two cascaded divide-by-two stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply. Next, we present a 40-Gb/s phase-locked clock and data recovery circuit incorporating a multiphase LC oscillator and a quarter-rate bang-bang phase detector. The oscillator is based on differential excitation of a closed-loop transmission line at evenly-spaced points, providing half-quadrature phases. The phase detector employs eight flipflops to sample the input every 12.5 ps, detecting data transitions while retiming and demultiplexing the data into four 10-Gb/s outputs. Fabricated in 0.18-um CMOS technology, the circuit produces a clock jitter of 0.9 ps-rms and 9.67 ps-pp with a PRBS of 2^31-1 while consuming 144 mW from a 2-V supply. Finally, a large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts such characteristics of clock and data recovery circuits as jitter transfer, jitter tolerance, jitter generation, bit error rate, and capture range. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander phase detector and an LC oscillator.

High-speed CMOS circuits for gigabit ethernet on copper wire

The next generation of local area networks (LANs) operates at data rates of up to several hundred megabits, or gigabits per second. In order to minimize the cost, use of the existing unshielded twisted-pair cable (similar to telephone copper wire) to connect the network terminals to central hubs is desirable. Among all of the LAN standards, Gigabit Ethernet on category 5 unshielded twisted pair (UTP) is the most popular and economical, since it is the next generation standard of commonly-used 10/100Base-T Ethernet. Due to the high data bandwidth on medium-quality copper line, and simultaneous data transmission on four twisted-pair cables, advanced signal processing such as channel equalization and echo/crosstalk cancellation is required to recover the signal from noisy channels. In order to meet the stringent bit-error-rate specifications of Gigabit Ethernet, designers of 1000Base-T must use complex digital signal processing as well as high resolution A/D converters to reduce impairments due to highly-corrupted channels. Until now, full digital signal processing has been considered the only possible solution to implement 1000Base-T transceivers. This research has investigated analog adaptive circuits to cancel noise and perform channel equalization in the analog front end. In addition to the circuit implementation, a custom C program is written to emulate the transceiver in order to determine the specifications of each analog building block. An adaptive mixed-signal echo canceller and a linear channel equalizer are proposed in this work to boost the signal-to-noise ratio. With the aid of these two building blocks, the A/D converter design requirement and the digital signal processor complexity are both reduced. In contrast to fully digital or analog implementations, the Gigabit Ethernet transceiver can be implemented by lower power consumption and smaller silicon die size with this hybrid architecture.

A low-power 2.4-GHz CMOS transceiver for wireless LAN applications

The rapid increase in the demand for RF transceivers used in wireless LAN systems such as Bluetooth and IEEE 802.11b has motivated extensive research on low-power solutions. This research deals with architecture, circuit, and device design for such applications. A multistandard CMOS transceiver incorporates low-power RF and analog techniques while operating with both frequency-hopped and direct-sequence systems. Using a single 1.6-GHz synthesizer, the circuit incorporates two downconversion and upconversion stages while providing on-chip image-rejection filtering. The transceiver employs on-chip stacked inductors extensively. With a modification of stacked spirals, the self-resonance frequencies increase by 100%, allowing high value inductors. Realized in a 0.25-um digital CMOS technology, the transceiver (excluding the synthesizer) consumes 17.5 mW from a 2.5-V supply.

High-speed clock and data recovery circuits for random non-return-to-zero data

The rapid increase of real-time audio and video transport over the internet has led to a global demand for high-speed serial-data communication networks. To accommodate the required bandwidth, an increasing number of wide area networks (WANs) and local area networks (LANs) are converting the transmission medium from a copper wire to fiber. This trend motivates research on low-cost, low-power integrated fiber-optic receivers. A critical task in such receivers is the recovery of the clock embedded in the non-return-to-zero (NRZ) serial-data stream. The recovered clock both removes the jitter and distortion in the data and retimes it for further processing. The research objective of this thesis is to analyze, design, and implement highspeed clock and data recovery circuits for 2.5-Gb/s optical fiber receivers that can be readily implemented in an integrated, low-cost, low-power CMOS technology. Our primary contributions to this research include the design methodology and implementation of two clock recovery circuits fabricated in both 0.4-um and 0.25-um digital CMOS technologies without the aide of external references. The circuit designed in the 0.4-um CMOS is limited by the achievable technology bandwidth. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide tuning range. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS of length 2^7-1. The core circuit dissipates a total power of 33.5 mW from 3.3-V supply and occupies an area of 0.8 x 0.4 mm^2. The system design in the 0.25-um CMOS includes both a frequency-locked loop (FLL) loop as well as a phase-locked loop (PLL) to increase the frequency acquisition range of the circuit with no external reference. To achieve a wide tuning range with low phase noise, an LC-oscillator is employed with a digital capacitor array. The recovered clock exhibits an rms jitter of 5.1 ps for a PRBS of length 2^23-1. This circuit core dissipates 55 mW of power from a 2.5 V supply and occupies a core area of 0.9 x 0.6 mm^2.

A 2-GHz CMOS image-reject receiver with sign-sign LMS calibration

This dissertation describes a sign-sign least-mean squares (LMS) technique to calibrate gain and phase errors in the signal path of a Weaver image-reject receiver. The calibration occurs at startup and the results are stored digitally, allowing continuous signal reception thereafter. Fabricated in a standard digital 0.25-um CMOS technology, the receiver achieves an image-rejection ratio of 57 dB after calibration, a noise figure of 5.2 dB, and an IIP3 of −17 dBm. The circuit consumes 55 mW in calibration mode and 50 mW in normal receiver mode from a 2.5-V power supply. The prototype occupies an area of 1.23 x 1.84 mm^2.

A 10-Gb/s CMOS clock and data recovery circuit

With the exponential growth of the number of Internet nodes, the volume of the data transported on the backbone has increased with the same trend. The load of the global Internet backbone will soon increase to tens of terabits per second. This indicates that the backbone bandwidth requirements will increase by a factor of 50 to 100 every seven years. Transportation of such high volumes of data requires suitable media with low loss and high bandwidth. Among the available transmission media, optical fibers achieve the best performance in terms of loss and bandwidth. High-speed data can be transported over hundreds of kilometers of single-mode fiber without significant loss in signal integrity. These fibers progressively benefit from reduction of cost and improvement of performance. Meanwhile, the electronic interfaces used in an optical network are not capable of exploiting the ultimate bandwidth of the fiber, limiting the throughput of the network. Different solutions at both the system and the circuit levels have been proposed to increase the data rate of the backbone. System-level solutions are based on the utilization of wave-division multiplexing (WDM), using different colors of light to transmit several sequences simultaneously. In parallel with that, a great deal of effort has been put into increasing the operating rate of the electronic transceivers using highly-developed fabrication processes and novel circuit techniques. The design of the clock and data recovery (CDR) circuit is the most challenging part of building a high-speed optical transceiver because of the complexity of this block. In this dissertation, the design and experimental results of two CDR circuits are described. Both the circuits achieve a high operating speed by employing the concept of "half rate", meaning that the clock frequency is half the data rate. Furthermore, broadband circuit techniques including wideband amplification and highspeed matched filtering are described in this dissertation. The two circuits benefit from two major techniques for phase detection, namely linear and binary. The design of the linear phase detector is based on a new technique that allows a fast speed and low power consumption because of its simplicity. The new binary phase/frequency detector provides a wide capture range and a phase error signal that is only revalidated at data transitions. Furthermore, the design of the CDR circuits involves utilization of two major types of voltage-controlled oscillators, which are ring and LC-tuned. The ring oscillator described in this work achieves a wide tuning range and low power consumption. The LC oscillator benefits from a new topology that provides multiple phases with low jitter.

An 8-bit 150-MHz CMOS A/D converter

High-speed analog-to-digital converters (ADCs) with resolutions of 8 bits find wide application in instrumentation and communication systems. For example, portable digital oscilloscopes use 8-bit ADCs with sampling rates above one hundred megahertz. Also, the Gigabit Ethernet standard with CAT-5 copper cable requires four 125-MHz ADCs having a resolution of 7 to 8 bits to perform the front-end analog-to-digital data conversion. This dissertation presents an 8-bit, 5-stage interleaved and pipelined ADC that performs analog processing only by means of open-loop circuits such as differential pairs and source followers, thereby achieving a high conversion rate. The concept of "sliding interpolation" is proposed to obviate the need for a large number of comparators or interstage digital-to-analog converters and residue amplifiers. The pipelining incorporates distributed sampling between the stages so as to relax the linearity-speed trade-offs in the sample-and-hold functions. This work also introduces a "clock edge reassignment" technique that suppresses timing mismatch issues in interleaved systems. Moreover, in order to reduce the integral nonlinearity error (INL) with negligible speed or power penalty, a "reinterpolation" method is proposed. Fabricated in a 0.6-um CMOS technology, the ADC achieves a DNL of 0.62 LSB, INL of 1.24 LSB, SFDR of 50 dB, and SNDR of 43.7 dB at 150 MHz sampling rate with low input frequencies. When input frequency is at 70 MHz, SNDR of 40 dB is attained. The converter draws 395 mW from a 3.3-V supply and occupies an area of 1.2 x 1.5 mm^2.